On 31 January 2017 at 15:15, Wei Huang <w...@redhat.com> wrote:
> This patch adds support for AArch64 register PMSELR_EL0. The existing
> PMSELR definition is revised accordingly.
>
> Signed-off-by: Wei Huang <w...@redhat.com>
> ---
> target/arm/cpu.h | 1 +
> target/arm/helper.c | 25 ++++++++++++++++++++-----
> 2 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 39bff86..8a82c73 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -309,6 +309,7 @@ typedef struct CPUARMState {
> uint32_t c9_pmovsr; /* perf monitor overflow status */
> uint32_t c9_pmxevtyper; /* perf monitor event type */
> uint32_t c9_pmuserenr; /* perf monitor user enable */
> + uint64_t c9_pmselr; /* perf monitor counter selection register */
> uint32_t c9_pminten; /* perf monitor interrupt enables */
> union { /* Memory attribute redirection */
> struct {
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index c23df1b..67520ea 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -975,6 +975,17 @@ static uint64_t pmccntr_read(CPUARMState *env, const
> ARMCPRegInfo *ri)
> return total_ticks - env->cp15.c15_ccnt;
> }
>
> +static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
> +{
> + /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
> + * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
> + * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
> + * accessed.
> + */
> + env->cp15.c9_pmselr = value & 0x1f;
> +}
> +
> static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> @@ -1194,12 +1205,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> /* Unimplemented so WI. */
> { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
> .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
> - /* Since we don't implement any events, writing to PMSELR is
> UNPREDICTABLE.
> - * We choose to RAZ/WI.
> - */
> { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
> - .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
> - .accessfn = pmreg_access },
> + .access = PL0_RW, .type = ARM_CP_ALIAS,
> + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
> + .accessfn = pmreg_access, .writefn = pmselr_write,
> + .raw_writefn = raw_write},
> + { .name = "PMSELR_EL0", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 5,
> + .access = PL0_RW, .accessfn = pmreg_access,
> + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmselr),
> + .writefn = pmselr_write, .raw_writefn = raw_write, },
> #ifndef CONFIG_USER_ONLY
> { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
> .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
> --
> 1.8.3.1
>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
