[Qemu-devel] [RFC PATCH 7/9] spapr: Set ISA 3.00 radix and hash bits in OV5

[Sam Bobroff]

Set new option vector 5 bits to indicate KVM support for in-memory
radix or hash modes and related options. The existing logic will
propagate the results back to the guest in the device tree. This
allows guests to perform client architecture support negotiation on
the new radix and hash MMU modes and will cause ISA 3.00 guests to
start using h_register_process_table().

Signed-off-by: Sam Bobroff <sam.bobr...@au1.ibm.com>
---
 hw/ppc/spapr.c              | 8 ++++++++
 include/hw/ppc/spapr_ovec.h | 6 ++++++
 2 files changed, 14 insertions(+)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 1411e470c0..c6a3a638cd 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1862,6 +1862,14 @@ static void ppc_spapr_init(MachineState *machine)
     }
 
     spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
+    if (kvmppc_has_cap_mmu_radix()) {
+        spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX);
+    }
+    if (kvmppc_has_cap_mmu_hash()) {
+        spapr_ovec_set(spapr->ov5, OV5_MMU_HASH);
+    }
+    spapr_ovec_set(spapr->ov5, OV5_SEG_HCALL);
+    spapr_ovec_set(spapr->ov5, OV5_SHOOTDOWN);
 
     /* advertise support for dedicated HP event source to guests */
     if (spapr->use_hotplug_event_source) {
diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h
index 0f14753ff8..0a77e2a14b 100644
--- a/include/hw/ppc/spapr_ovec.h
+++ b/include/hw/ppc/spapr_ovec.h
@@ -47,6 +47,12 @@ typedef struct sPAPROptionVector sPAPROptionVector;
 #define OV5_DRCONF_MEMORY       OV_BIT(2, 2)
 #define OV5_FORM1_AFFINITY      OV_BIT(5, 0)
 #define OV5_HP_EVT              OV_BIT(6, 5)
+#define OV5_INT_ARCH_LVL        OV_BIT(23, 7)
+#define OV5_MMU_RADIX           OV_BIT(24, 0)
+#define OV5_MMU_HASH            OV_BIT(24, 1)
+#define OV5_SEG_RADIX           OV_BIT(24, 2)
+#define OV5_SEG_HCALL           OV_BIT(24, 3)
+#define OV5_SHOOTDOWN           OV_BIT(24, 4)
 
 /* interfaces */
 sPAPROptionVector *spapr_ovec_new(void);
-- 
2.11.0