On Tue, Feb 7, 2017 at 8:09 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 31 January 2017 at 16:22, <vijay.kil...@gmail.com> wrote: >> From: Vijaya Kumar K <vijaya.ku...@cavium.com> >> >> To Save and Restore ICC_SRE_EL1 register Add ICC_SRE_EL1 register >> to vmstate and GICv3CPUState struct. >> >> Signed-off-by: Vijaya Kumar K <vijaya.ku...@cavium.com> >> --- >> hw/intc/arm_gicv3_common.c | 1 + >> include/hw/intc/arm_gicv3_common.h | 1 + >> 2 files changed, 2 insertions(+) >> >> diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c >> index 0f8c4b8..f3245d9 100644 >> --- a/hw/intc/arm_gicv3_common.c >> +++ b/hw/intc/arm_gicv3_common.c >> @@ -68,6 +68,7 @@ static const VMStateDescription vmstate_gicv3_cpu = { >> VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState), >> VMSTATE_UINT32(gicr_nsacr, GICv3CPUState), >> VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL), >> + VMSTATE_UINT64(icc_sre_el1, GICv3CPUState), >> VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2), >> VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState), >> VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3), >> diff --git a/include/hw/intc/arm_gicv3_common.h >> b/include/hw/intc/arm_gicv3_common.h >> index 341a311..183c7f8 100644 >> --- a/include/hw/intc/arm_gicv3_common.h >> +++ b/include/hw/intc/arm_gicv3_common.h >> @@ -166,6 +166,7 @@ struct GICv3CPUState { >> uint8_t gicr_ipriorityr[GIC_INTERNAL]; >> >> /* CPU interface */ >> + uint64_t icc_sre_el1; >> uint64_t icc_ctlr_el1[2]; >> uint64_t icc_pmr_el1; >> uint64_t icc_bpr[3]; > > This breaks migration compatibility for TCG using GICv3; you > need to do something here with a VMState subsection so > the new register is only transferred if it's non-zero.
So, you mean to put a check in kvm_arm_gicv3_put() and kvm_arm_gicv3_get() to check for non-zero value? icc_sre_el1 is always non-zero reset to 0xf in TCG and 0x7 in KVM mode. > > thanks > -- PMM