On 02/18/2017 01:38 PM, Peter Maydell wrote: > On 18 February 2017 at 17:45, Michael Davidsaver <mdavidsa...@gmail.com> > wrote: >> On 02/16/2017 09:11 AM, Peter Maydell wrote: >>> I haven't actually checked real hardware behaviour, but I think >>> we can fairly safely implement this as not checking the IPSR >>> exception field. (We might as well go with the "reads 1 in >>> handler mode" choice of UNKNOWN that the M3 documents, though.) >> >> For what it's worth, I dug up my TI TM4C1294 eval board and re-ran >> test10.c [1] which is designed to probe this behavior by nesting >> exceptions PendSV within SVC. RETTOBASE is 0x800 in ICSR. > > That's a Cortex-M4. From the test it looks like it > has a different choice of UNKNOWN behaviour for > the value in Handler mode, so real code in the field > isn't going to be relying on that and it doesn't > matter what we choose.
I've been away from arm/m for too long to claim any detailed knowledge of the documentation. My intent here is only to provide a data point w/ real hardware, not to interpret it. > I don't think the test looks at the "what happens if the > exception in the IPSR exception field isn't actually > active" case, right? Correct.