On 20 February 2017 at 06:21, Vijay Kilari <vijay.kil...@gmail.com> wrote: > Hi Peter, > > On Fri, Feb 17, 2017 at 7:25 PM, Peter Maydell <peter.mayd...@linaro.org> > wrote: [on the guest-visible ICC_SRE_EL1 value] >> Is there a situation where KVM might allow a value other >> than 0x7? > > In KVM, the SRE_EL1 value is 0x1. During save, value > read from KVM is 0x1 though we reset to 0x7.
0x1 meanss "System Register Interface enabled, IRQ bypass enabled, FIQ bypass enabled". This seems rather a weird setting, because it means "the GICv3 CPU interface functionality is disabled and the GICv3 should signal interrupts via legacy IRQ and FIQ". Does KVM really support IRQ/FIQ bypass and does Linux really leave it enabled rather than turning it off by writing the value to 1? My expectation was that the KVM GICv3 emulation would make these bits RAO/WI like the TCG implementation. Is there maybe a bug in the kernel side where it doesn't implement bypass but has made these bits be RAZ/WI rather than RAO/WI ? thanks -- PMM
