On 13 February 2017 at 14:44, Cédric Le Goater <c...@kaod.org> wrote: > The setting of the DRAM address of the DMA transaction depends on the > DRAM base address of the SoC. Let's add a property to give this > information to the SMC controller model. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> > Reviewed-by: Joel Stanley <j...@jms.id.au> > Reviewed-by: Andrew Jeffery <and...@aj.id.au> > --
This seems a bit weird -- what does it actually do in hardware? (Does it really have the ability to dma anywhere in the address space and just use an odd base address, or is it DMA'ing to a more restricted address space?) thanks -- PMM
