On 02/22/2017 10:03 PM, Nikunj A Dadhania wrote:
Richard Henderson <r...@twiddle.net> writes:
On 02/22/2017 08:29 PM, Nikunj A Dadhania wrote:
For 64-bit mode if the register RA contains 0x8000_0000_0000_0000, OV
and OV32 are set to 1.
For 32-bit mode if the register RA contains 0x8000_0000, OV and OV32 are
set to 1.
Use the tcg-ops for negation (neg_tl) and drop gen_op_arith_neg() as
nego was the last user.
Signed-off-by: Nikunj A Dadhania <nik...@linux.vnet.ibm.com>
---
target/ppc/translate.c | 26 +++++++++++++++++---------
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eecdfe9..2a9f508 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1473,14 +1473,6 @@ static void gen_subfic(DisasContext *ctx)
}
/* neg neg. nego nego. */
-static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
-{
- TCGv zero = tcg_const_tl(0);
- gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- zero, 0, 0, compute_ov, Rc(ctx->opcode));
- tcg_temp_free(zero);
-}
-
static void gen_neg(DisasContext *ctx)
{
tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
@@ -1491,7 +1483,23 @@ static void gen_neg(DisasContext *ctx)
static void gen_nego(DisasContext *ctx)
{
- gen_op_arith_neg(ctx, 1);
+ TCGv t0 = tcg_temp_new();
+ TCGv zero = tcg_const_tl(0);
+
+ if (NARROW_MODE(ctx)) {
+ tcg_gen_xori_tl(t0, cpu_gpr[rA(ctx->opcode)], INT32_MIN);
+ } else {
+ tcg_gen_xori_tl(t0, cpu_gpr[rA(ctx->opcode)], (target_ulong)INT64_MIN);
+ }
+
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_ov, t0, zero);
+ tcg_gen_mov_tl(cpu_ov32, cpu_ov);
I think we just now covered this is wrong in the v1 thread.
With respect to the simulator, right?
I will restore the same neg/nego behaviour using subf, as OV/OV32 will
be updated as per the simulator.
Yes. It's the only solution that makes sense to me.
r~
