On 25 March 2017 at 02:22, Wangjintang <wangjint...@huawei.com> wrote: > the patch regard the prefetch as load instruction, at the same time > don't affect rm/rt register. Only the PRFM instruction been emitted to > intermediate code and do a really load, then we can get the memory > address relative to the prefetch instruction. Because the rm/rt register > don't been modified, so the application can run correctly.
It will still fault if the address is not valid, which is not a permitted behaviour. > In our case, we need all the instruction trace & ld/st instruction's > access memory address, the trace as the input for chip cycle-accurate > model. Similar with flexus + qemu. > Current code that skip generate prefetch instructions' intermediate code, > So we can get prefetch instruction, but can't get the prefetch instruction > relative memory address. I understand the use case you would like, but if we want to support that kind of thing we should do it with a much more significant and consistent degree of support for tracing of guest code actions, not with a small ad-hoc change that happens to fix the immediate thing you're running into for your specific problem. thanks -- PMM
