This patch seems correct:
$ docker run -it -v `pwd`:`pwd` -w `pwd` petersenna/coccinelle --sp-file
scripts/coccinelle/tcg_gen_extract.cocci --macro-file
scripts/cocci-macro-file.h --dir target/sparc
init_defs_builtins: /usr/lib64/coccinelle/standard.h
init_defs: scripts/cocci-macro-file.h
HANDLING: target/sparc/helper.c
HANDLING: target/sparc/ldst_helper.c
HANDLING: target/sparc/gdbstub.c
HANDLING: target/sparc/translate.c
candidate at target/sparc/translate.c:404
op_size: tl/tl (same)
low_bits: 1 (value: 0x1)
len: 0x1
len_bits == low_bits
candidate IS optimizable
candidate at target/sparc/translate.c:383
op_size: tl/tl (same)
low_bits: 1 (value: 0x1)
len: 0x1
len_bits == low_bits
candidate IS optimizable
candidate at target/sparc/translate.c:397
op_size: tl/tl (same)
low_bits: 1 (value: 0x1)
len: 0x1
len_bits == low_bits
candidate IS optimizable
candidate at target/sparc/translate.c:390
op_size: tl/tl (same)
low_bits: 1 (value: 0x1)
len: 0x1
len_bits == low_bits
candidate IS optimizable
candidate at target/sparc/translate.c:641
op_size: tl/tl (same)
low_bits: 31 (value: 0x7fffffff)
len: 0x7fffffff
len_bits == low_bits
candidate IS optimizable
On 05/10/2017 05:05 PM, Philippe Mathieu-Daudé wrote:
Applied using Coccinelle script.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/sparc/translate.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index aa6734d54e..a92b5c425c 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -380,29 +380,25 @@ static inline void gen_goto_tb(DisasContext *s, int
tb_num,
static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 0x1);
}
static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 0x1);
}
static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 0x1);
}
static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 0x1);
}
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -638,8 +634,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv
src2)
// env->y = (b2 << 31) | (env->y >> 1);
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
tcg_gen_shli_tl(r_temp, r_temp, 31);
- tcg_gen_shri_tl(t0, cpu_y, 1);
- tcg_gen_andi_tl(t0, t0, 0x7fffffff);
+ tcg_gen_extract_tl(t0, cpu_y, 1, 0x7fffffff);
tcg_gen_or_tl(t0, t0, r_temp);
tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
