Please see bonito64_pcibios_config_access() in arch/mips/pci/ops-bonito64.c of Linux kernel code. You will find something useful.
On Thu, Oct 28, 2010 at 12:54 PM, Michael S. Tsirkin <m...@redhat.com> wrote: > On Thu, Oct 28, 2010 at 08:57:01AM +0800, chen huacai wrote: >> Because the code in PMON and Linux kernel use these bits to verify r/w >> operations. If one of them is 1 after r/w, PMON and Linux will >> consider r/w has failed. > > Where's that code in Linux? > >> I guess that software will not set them to 1, because it is set by >> hardware when operation fails. > > So I guess just making these write 1 to clear according to spec will work? > >> On Thu, Oct 28, 2010 at 12:12 AM, Michael S. Tsirkin <m...@redhat.com> wrote: >> > I see code in bonito.c that clears bits: >> > PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT >> > on each read and write. >> > >> > However >> > 1. I don't see anything in code that would set these bits >> > 2. The PCI spec says this about the status register: >> > >> > Reads to this register behave normally. Writes are slightly >> > different in >> > that bits can be reset, but not set. A one bit is reset (if it is >> > not >> > read-only) whenever the register is written, and the write data in >> > the >> > corresponding bit location is a 1. For instance, to clear bit 14 >> > and not >> > affect any other bits, write the value 0100_0000_0000_0000b to the >> > register. >> > >> > while the code in bonito.c resets the bits to 0 on each write. >> > >> > Comments? >> > >> > -- >> > MST >> > >> >> >> >> -- >> Huacai Chen > -- Huacai Chen
