On 08/02/2017 09:43 AM, Peter Maydell wrote: > Tighten up the T32 decoder in the places where new v8M instructions > will be: > * TT/TTT/TTA/TTAT are in what was nominally LDREX/STREX r15, ... > which is UNPREDICTABLE: > make the UNPREDICTABLE behaviour be to UNDEF > * BXNS/BLXNS are distinguished from BX/BLX via the low 3 bits, > which in previous architectural versions are SBZ: > enforce the SBZ via UNDEF rather than ignoring it, and move > the "ARCH(5)" UNDEF case up so we don't leak a TCG temporary > * SG is in the encoding which would be LDRD/STRD with rn = r15; > this is UNPREDICTABLE and we currently UNDEF: > move this check further up the code so that we don't leak > TCG temporaries in the UNDEF case and have a better place > to put the SG decode. > > This means that if a v8M binary is accidentally run on v7M > or if a test case hits something that we haven't implemented > yet the behaviour will be obvious (UNDEF) rather than obscure > (plough on treating it as a different instruction). > > In the process, add some comments about the instruction patterns > at these points in the decode. Our Thumb and ARM decoders are > very difficult to understand currently, but gradually adding > comments like this should help to clarify what exactly has > been decoded when. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/translate.c | 48 +++++++++++++++++++++++++++++++++++++++--------- > 1 file changed, 39 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
