On Tue, Sep 19, 2017 at 03:46:20PM +0200, Cédric Le Goater wrote: > On 09/19/2017 04:39 AM, David Gibson wrote: > > On Mon, Sep 11, 2017 at 07:12:17PM +0200, Cédric Le Goater wrote: > >> The XIVE interrupt controller of the POWER9 uses a set of tables to > >> redirect exception from event sources to CPU threads. Among which we > >> choose to model : > >> > >> - the State Bit Entries (SBE), also known as Event State Buffer > >> (ESB). This is a two bit state machine for each event source which > >> is used to trigger events. The bits are named "P" (pending) and "Q" > >> (queued) and can be controlled by MMIO. > >> > >> - the Interrupt Virtualization Entry (IVE) table, also known as Event > >> Assignment Structure (EAS). This table is indexed by the IRQ number > >> and is looked up to find the Event Queue associated with a > >> triggered event. > > > > Both the above are one entry per irq source, yes? What's the > > rationale for having them as parallel tables, rather than bits in a > > single per-source structure? > > For the sPAPR machines, yes, we could use a struct to hold both > information. But these tables are defined in the HW specs and > are used as such by the PowerNV platform in skiboot. They are > registered by the firmware for the use of the XIVE interrupt > controller. > > When we model XIVE for PowerNV, it would be preferable to have > common definitions for these tables I think.
Ok, that seems like a reasonable case.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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