On 09/27/2017 10:00 AM, David Hildenbrand wrote: > Background: s390x implements Low-Address Protection (LAP). If LAP is > enabled, writing to effective addresses (before any transaltion) > 0-511 and 4096-4607 triggers a protection exception. > > So we have subpage protection on the first two pages of every address > space (where the lowcore - the CPU private data resides). > > By immediately invalidating the write entry but allowing the caller to > continue, we force every write access onto these first two pages into > the slow path. we will get a tlb fault with the specific accessed > addresses and can then evaluate if protection applies or not. > > We have to make sure to ignore the invalid bit if tlb_fill() succeeds.
This is similar to a scheme I proposed to PMM wrt handling ARM v8M translation. Reusing TLB_INVALID_MASK would appear to work, but I wonder if it wouldn't be clearer to use another bit. I believe I had proposed a TLB_FORCE_SLOW_MASK. Thoughts, Peter? r~
