On 11/02/2017 12:33 PM, Peter Maydell wrote: > For AArch32 LDREXD and STREXD, architecturally the 32-bit word at the > lowest address is always Rt and the one at addr+4 is Rt2, even if the > CPU is big-endian. Our implementation does these with a single > 64-bit store, so if we're big-endian then we need to put the two > 32-bit halves together in the opposite order to little-endian, > so that they end up in the right places. We were trying to do > this with the gen_aa32_frob64() function, but that is not correct > for the usermode emulator, because there there is a distinction > between "load a 64 bit value" (which does a BE 64-bit access > and doesn't need swapping) and "load two 32 bit values as one > 64 bit access" (where we still need to do the swapping, like > system mode BE32). > > Fixes: https://bugs.launchpad.net/qemu/+bug/1725267 > Cc: qemu-sta...@nongnu.org > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > Changes v1->v2: > * use correct "s->be_data == MO_BE" check for bigendian > * don't mangle the data from the atomic-cmpxchg before > comparing against expected value > * tcg_temp_free() the TCGv from gen_aa32_addr() > * name that TCGv "taddr" rather than "a"...
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
