default to SDHCI v2
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
hw/sd/sdhci-internal.h | 4 ++--
include/hw/sd/sdhci.h | 10 ++++++++++
hw/sd/sdhci.c | 5 ++++-
3 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index e941bc2386..7e4a9d79d1 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -210,9 +210,9 @@
/* Slot interrupt status */
#define SDHC_SLOT_INT_STATUS 0xFC
-/* HWInit Host Controller Version Register 0x0401 */
+/* HWInit Host Controller Version Register */
#define SDHC_HCVER 0xFE
-#define SD_HOST_SPECv2_VERS 0x2401
+#define SDHC_HCVER_VENDOR 0x24
#define SDHC_REGISTERS_MAP_SIZE 0x100
#define SDHC_INSERTION_DELAY (NANOSECONDS_PER_SECOND)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index a8ffac9dba..68f5902cdf 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -89,6 +89,9 @@ typedef struct SDHCIState {
/* Force Event Auto CMD12 Error Interrupt Reg - write only */
/* Force Event Error Interrupt Register- write only */
/* RO Host Controller Version Register always reads as 0x2401 */
+ struct {
+ uint8_t spec_version;
+ } capabilities;
} SDHCIState;
#define TYPE_PCI_SDHCI "sdhci-pci"
@@ -98,4 +101,11 @@ typedef struct SDHCIState {
#define SYSBUS_SDHCI(obj) \
OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI)
+/* Host Controller Specification Version */
+enum sdhci_spec_version {
+ SD_HOST_SPECv1_VERS = 0x00,
+ SD_HOST_SPECv2_VERS = 0x01,
+ SD_HOST_SPECv3_VERS = 0x02
+};
+
#endif /* SDHCI_H */
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 64a9b26e0d..926f6d1958 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -927,7 +927,8 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,
unsigned size)
ret = (uint32_t)(s->admasysaddr >> 32);
break;
case SDHC_SLOT_INT_STATUS:
- ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
+ ret = (SDHC_HCVER_VENDOR << 24) | (s->capabilities.spec_version << 16);
+ ret |= sdhci_slotint(s);
break;
default:
qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
@@ -1290,6 +1291,8 @@ const VMStateDescription sdhci_vmstate = {
/* Capabilities registers provide information on supported features of this
* specific host controller implementation */
static Property sdhci_properties[] = {
+ DEFINE_PROP_UINT8("sd-spec-version", SDHCIState,
+ capabilities.spec_version, SD_HOST_SPECv2_VERS),
DEFINE_PROP_UINT64("capareg", SDHCIState, capareg,
SDHC_CAPAB_REG_DEFAULT),
DEFINE_PROP_UINT64("maxcurr", SDHCIState, maxcurr, 0),
--
2.15.1
