On 11 January 2018 at 19:10, Richard Henderson <richard.hender...@linaro.org> wrote: > On 01/11/2018 10:06 AM, Peter Maydell wrote: >> On 18 December 2017 at 17:45, Richard Henderson >> <richard.hender...@linaro.org> wrote: >>> To be used to decode ARM SVE, but could be used for any 32-bit RISC. >>> It would need additional work to extend to insn sizes other than 32-bit. >> >> I guess we could make that extension without requiring all >> existing pattern files to be updated, right? > > Sure. I would expect that to be a command-line option for the script.
It occurs to me that we could just make it silently DTRT -- we want to check the bit count in patterns and so on to detect typos, but it would be a weird typo that was wrong by 8 bits, so as long as the patterns are all a multiple of 8 bits long we could accept them (and handle them in whatever way we find we need to handle mixed-length instruction sets). So we might not even need a command line option. thanks -- PMM
