Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> Acked-by: Alistair Francis <alistair.fran...@xilinx.com> --- Krzysztof kindly checked those values with Manaul, the Samsung datasheet :)
hw/arm/exynos4210.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index e8e1d81e62..e70e234f58 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -75,7 +75,6 @@ #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 /* SD/MMC host controllers */ -#define EXYNOS4210_SDHCI_CAPABILITIES 0x05E80080 #define EXYNOS4210_SDHCI_BASE_ADDR 0x12510000 #define EXYNOS4210_SDHCI_ADDR(n) (EXYNOS4210_SDHCI_BASE_ADDR + \ 0x00010000 * (n)) @@ -377,8 +376,26 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) BlockBackend *blk; DriveInfo *di; + /* Compatible with: + * - SD Host Controller Specification Version 2.0 + * - SDIO Specification Version 2.0 + * - MMC Specification Version 4.3 + * - SDMA + * - ADMA2 + * + * As this part of the Exynos4210 is not publically available, + * we used the "HS-MMC Controller S3C2416X RISC Microprocessor" + * public datasheet which is very similar (implementing + * MMC Specification Version 4.0 being the only difference noted) + */ dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); - qdev_prop_set_uint32(dev, "capareg", EXYNOS4210_SDHCI_CAPABILITIES); + qdev_prop_set_uint8(dev, "sd-spec-version", 2); + qdev_prop_set_uint8(dev, "timeout-freq", 0); + qdev_prop_set_uint8(dev, "max-frequency", 0); + qdev_prop_set_bit(dev, "suspend", true); + qdev_prop_set_bit(dev, "sdma", true); + qdev_prop_set_bit(dev, "adma1", false); + qdev_prop_set_bit(dev, "adma2", true); qdev_init_nofail(dev); busdev = SYS_BUS_DEVICE(dev); -- 2.15.1