On Wed, Jan 24, 2018 at 3:47 PM, Richard Henderson <richard.hender...@linaro.org> wrote: > On 01/24/2018 10:58 AM, Jim Wilson wrote: >> Although, looking at this again, I see another statement in a >> different place that says: >> >> Except when otherwise stated, if the result of a floating-point operation is >> NaN, it is the canonical NaN. The canonical NaN has a positive sign and all >> significand bits clear except the MSB, a.k.a. the quiet bit. For >> single-precision floating-point, this corresponds to the pattern >> 0x7fc00000. > Yes, I had read this before as well. I had assumed that your patch > constituted > an intended change to this text. > >> This could take a little time to sort out. > Ok. I don't see this as a blocking issue for merging.
So after looking at this a bit more, I've come to the conclusion that my patch to remove the default/canonical nan support from RISC-V qemu was wrong. We will have to fix this on the gcc/glibc side. Michael, please revert my change https://github.com/riscv/riscv-qemu/commit/4223d89b0c5c671332d66bcd649db5c6f46559f5 Jim