This patchset (when combined with my previous patchset "Translate based on TB flags, not CPUState") is a fix for https://bugs.launchpad.net/qemu/+bug/581335 where we were not getting the IT (conditional execution) bits in the CPSR right when we took an unexpected exception in Thumb mode.
The linux-user patch fixes an issue exposed by fixing this, where we weren't clearing the IT bits before entering the signal handler, so that if we took the signal inside an IT block the first part of the signal handler wouldn't be executed. The first two patches in the series and the long comment in patch 4 are aimed at making it a bit clearer how we handle the IT bits; it took me quite a long time to figure out exactly what the existing code was doing... Peter Maydell (4): target-arm: Remove redundant setting of IT bits before Thumb SWI target-arm: Refactor translation of exception generating instructions linux-user: ARM: clear the IT bits when invoking a signal handler target-arm: Restore IT bits when resuming after an exception linux-user/signal.c | 16 +++++---- target-arm/translate.c | 80 ++++++++++++++++++++++++++++++----------------- 2 files changed, 60 insertions(+), 36 deletions(-)
