On Thu, Feb 08, 2018 at 02:58:29PM +0000, Peter Maydell wrote:
> On 4 February 2018 at 20:41, Richard Braun <rbr...@sceen.net> wrote:
> > Consider that data is always immediately sent. As a result, keep
> > the SR_TXE and SR_TC bits always set. In addition, fix the reset value
> > of the USART status register.
> Do you know what the data sheet means when it says that TC
> can be cleared by "a read from the USART_SR register followed
> by a write to the USART_DR register" ?

It's meant for software either polling the TC bit or waiting for a
transmission complete interrupt. Once the bit is seen, the next
transmission automatically clears it.

> If we supported interrupts properly (which we don't seem to)
> I suspect we'd need something more than "TXE and TC are always set",
> or the guest would probably never clear the TXE and TC interrupts.

That's the idea of the patch. Since everything is currently synchronous,
there is no need for these transient states to even exist.

> The guest can clear the TC and TXE bits by writing to the USART_SR
> directly, so this code should set both of them, I think ?

Right, nice catch.

Richard Braun

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