This patchset is the result of comparing the registers listed in the v8M Arm ARM against what QEMU was implementing. It adds a collection of generally unexciting missing registers (most of which we can simply NOP or make reads-as-written). There are also a couple of bug fixes in there, of which the worst is the byte-to-interrupt-number conversions being completely wrong in several places.
Version 2 adds 3 new patches at the end: * we had a couple of things we were forgetting to migrate * implementation of MSPLIM and PSPLIM, which were the missing special registers I've updated the cache ID registers patch to use some constants for register bit fields; otherwise the first 8 patches are the same as v1. The derived-exceptions patches are in master now, so this should apply to master. thanks -- PMM Peter Maydell (11): hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling hw/intc/armv7m_nvic: Implement M profile cache maintenance ops hw/intc/armv7m_nvic: Implement v8M CPPWR register hw/intc/armv7m_nvic: Implement cache ID registers hw/intc/armv7m_nvic: Implement SCR target/arm: Implement writing to CONTROL_NS for v8M hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions target/arm: Add AIRCR to vmstate struct target/arm: Migrate v7m.other_sp target/arm: Implement v8M MSPLIM and PSPLIM registers target/arm/cpu.h | 35 ++++++++++++++++++ hw/intc/armv7m_nvic.c | 98 ++++++++++++++++++++++++++++++++++++++------------- target/arm/cpu.c | 28 +++++++++++++++ target/arm/helper.c | 56 +++++++++++++++++++++++++++++ target/arm/machine.c | 84 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 276 insertions(+), 25 deletions(-) -- 2.16.1