On Sat, Feb 10, 2018 at 8:42 AM, Richard Henderson < richard.hender...@linaro.org> wrote:
> On 02/07/2018 05:28 PM, Michael Clark wrote: > > create mode 100644 hw/riscv/Makefile.objs > > create mode 100644 hw/riscv/riscv_elf.c > > create mode 100644 hw/riscv/riscv_hart.c > > create mode 100644 hw/riscv/riscv_htif.c > > create mode 100644 hw/riscv/sifive_clint.c > > create mode 100644 hw/riscv/sifive_e300.c > > create mode 100644 hw/riscv/sifive_plic.c > > create mode 100644 hw/riscv/sifive_prci.c > > create mode 100644 hw/riscv/sifive_test.c > > create mode 100644 hw/riscv/sifive_u500.c > > create mode 100644 hw/riscv/sifive_uart.c > > create mode 100644 hw/riscv/spike_v1_09.c > > create mode 100644 hw/riscv/spike_v1_10.c > > create mode 100644 hw/riscv/virt.c > > I have no plans to review these last 9 patches. > They all look plausible to me, but I'm not so > up-to-date on best practices within hw/. > No problem. Thanks a lot for your help with reviewing disas, target/riscv and linux-user. The code is now in much much better shape than it was before. The patches that have been reviewed represent the bulk of the port (over ~10K LOC of the ~14K LOC in total). The remaining 11 or so patches are relatively small in comparison. We could submit the core of the port which would give us linux-user however it would be nice to get the spike machines and virt machine upstream. The spike v1.10 machine is required to run riscv-tests and the virt machine is being used by linux porters. BTW Let us know when the softfloat changes have landed. We could potentially point fmin/fmax at minnum/maxnum in the interim. In any case, we still have a reasonable amount of time left if we want to get in to the 2.12 release... I see that March 13th is the soft feature freeze: - https://wiki.qemu.org/Planning/2.12
