On 15 February 2018 at 22:27, Alistair Francis <alistai...@gmail.com> wrote:
> On Tue, Feb 13, 2018 at 12:54 PM, Richard Braun <rbr...@sceen.net> wrote:
>> I/O currently being synchronous, there is no reason to ever clear the
>> SR_TXE bit. However the SR_TC bit may be cleared by software writing
>> to the SR register, so set it on each write.
>> In addition, fix the reset value of the USART status register.
>> Signed-off-by: Richard Braun <rbr...@sceen.net>
> Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com>

Applied to target-arm.next, thanks.

-- PMM

Reply via email to