On 17 February 2018 at 18:23, Richard Henderson
<richard.hender...@linaro.org> wrote:
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/translate-sve.c | 51
> ++++++++++++++++++++++++++++++++++++++++++++++
> target/arm/sve.decode | 9 ++++++++
> 2 files changed, 60 insertions(+)
> +static void trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a, uint32_t
> insn)
> +{
> + TCGv_i64 addr;
> + int msz = dtype_msz(a->dtype);
> +
> + if (a->rm == 31) {
> + unallocated_encoding(s);
> + return;
> + }
> +
> + addr = new_tmp_a64(s);
> + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), msz);
> + tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
> + do_ldrq(s, a->rd, a->pg, addr, msz);
> +}
> +
> +static void trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a, uint32_t
> insn)
> +{
> + TCGv_i64 addr = new_tmp_a64(s);
> +
> + tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 16);
It confused me initially here that the calculation of the offset
for the +immediate and the +scalar cases isn't the same, but that
is indeed what the architecture does. Maybe
/* Unlike LD1RQ_zprr, offset scaling is constant rather
* than based on msz.
*/
?
> + do_ldrq(s, a->rd, a->pg, addr, dtype_msz(a->dtype));
> +}
>
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
