Hi David, On Mon, Mar 05, 2018 at 05:22:33PM +1100, David Gibson wrote: > On Wed, Feb 28, 2018 at 09:51:37AM +0800, wei.guo.si...@gmail.com wrote: > > From: Simon Guo <wei.guo.si...@gmail.com> > > > > During migration, cpu_post_load() will use msr_mask to determine which > > PPC MSR bits will be sync to the target side. Hardware Transaction > > Memory(HTM) has been supported since Power8. This patch adds TM/TS bits > > into msr_mask for Power8, so that transactional application can be > > migrated across qemu. > > > > Signed-off-by: Simon Guo <wei.guo.si...@gmail.com> > > Sorry I've taken a while to respond to this. > > This addresses a real bug, but doesn't get the details quite right. > > First, the MSR_TM bit is *already* included in the msr_mask for POWER8 > (it's a little above the context for this patch), though TS0 and TS1 > were not. > > Second, all MSR bits are sent to the far side, it's just that without > them in the MSR mask they'll be dropped instead of re-inserted into > KVM. That's the only reason the msr_mask is relevant to KVM (and TCG > doesn't support HTM anyway). The commit message needs to make that clearer. >
Thanks for the comments. I have sent v2 to correct the above. Regards, - Simon
