On Wed, Mar 7, 2018 at 12:09 AM, Peter Maydell <peter.mayd...@linaro.org>

> On 6 March 2018 at 01:30, Michael Clark <m...@sifive.com> wrote:
> > I've squashed the trivial spike rename fix and rebased against master as
> of
> > commit f2bb2d14c2958f3f5aef456bd2cdb1ff99f4a562 Merge remote-tracking
> branch
> > 'remotes/stefanha/tags/block-pull-request' into staging. See here:
> >
> > - https://github.com/riscv/riscv-qemu/releases/tag/riscv-
> qemu-upstream-v8.1
> OK. In the interests of getting the RISC-V port into upstream before
> the upcoming softfreeze deadline (which is next Tuesday)[*], please
> can you:
>  * make sure you have a signed tag and send it as a proper pull request
> email
>  * send your other queued changes to the mailing list as a patch series
>    so they can be reviewed
>  * work with Igor to identify the changes you need to make for the
>    CPU type registering issue he's raised, and then send a patch for that

I believe I have done all 3 now.

I would also like to forward port the change to implement IEEE-754
minimumNumber/maximumNumber to fix our fmin/fmax regression. I dropped the
patch due to conflicting changes in softfloat. With that change we are
passing all of the current riscv-tests for the Base ISA, with the exception
of returning NaN for SP floating point ops on DP register values. RISC-V
has a NaN boxing scheme to identify the type of floating point values in
memory, unlike SSE registers where the upper bits are undefined, RISC-V
requires the FP register file to "box" SP inside of a wider -NaN. i.e. the
upper 32 bits are all 1s. This was done to support type identification for
FPUs that work with a recoded internal format. The mechanism is described
in "9.2 NaN Boxing of Narrower Values" in the draft RISC-V ISA Manual. The
essence is to solve the context switch issue where FSD (Store Double) is
used to save values from the register file. By defining the upper bits as
Boxed within a NaN, the spec solves a binary compatibility issue between
different RISC-V implementations. For QEMU RISC-V, we'll need to add checks
on all SP floating point operations to check that the value is canonically
boxed, otherwise return a NaN (in the corner case where incorrect code
performs a SP operation on an FPU register containing a DP value). Once we
fix this issue, and minimumNumber/maximumNumber, QEMU RISC-V will be
passing 100% of the current Base ISA tests.

[*] For us, 'softfreeze' means that any new features must be in a pull
> request on the mailing list by that date; after that only bugfixes.
> Hardfreeze and the first rc candidate build is a week after that.
> See https://wiki.qemu.org/Planning/2.12 for other dates.
> thanks
> -- PMM

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