On 16 March 2018 at 20:31, Aaron Lindsay <alind...@codeaurora.org> wrote:
> Adding an array for v7VE+ CP registers was necessary so that PMOVSSET
> wasn't defined for all v7 processors.
>
> Signed-off-by: Aaron Lindsay <alind...@codeaurora.org>
> ---
> target/arm/helper.c | 32 +++++++++++++++++++++++++++++++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index d4f06e6..f5e800e 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1241,9 +1241,17 @@ static void pmcntenclr_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + value &= PMU_COUNTER_MASK(env);
> env->cp15.c9_pmovsr &= ~value;
> }
>
> +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
> +{
> + value &= PMU_COUNTER_MASK(env);
> + env->cp15.c9_pmovsr |= value;
> +}
> +
> static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> @@ -1406,7 +1414,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
> .writefn = pmcntenclr_write },
> { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
> - .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
> + .access = PL0_RW, .fieldoffset = offsetoflow32(CPUARMState,
> cp15.c9_pmovsr),
> .accessfn = pmreg_access,
> .writefn = pmovsr_write,
> .raw_writefn = raw_write },
This change is half of a bug fix (the other half being to make the
field in the CPU struct be uint64_t rather than uint32_t). That
bug fix should be in a patch of its own.
pmuserenr has the same bug (uint32_t state field accessed by
a STATE_AA64 sysreg).
thanks
-- PMM
