The ARM PMU implementation currently contains a basic cycle counter, but it is often useful to gather counts of other events and filter them based on execution mode. These patches flesh out the implementations of various PMU registers including PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent arbitrary counter types, implement mode filtering, send interrupts on counter overflow, and add instruction, cycle, and software increment events.
Since v4 I've added improved V7VE handling with Peter's direction, fixed up a few patch staging issues, and fixed a bug causing cycle counter overflow to be checked every instruction. -Aaron Aaron Lindsay (13): target/arm: Reorganize PMCCNTR accesses target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Allow AArch32 access for PMCCFILTR target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions target/arm: Remove redundant DIV detection for KVM target/arm: Implement PMOVSSET target/arm: Add array for supported PMU events, generate PMCEID[01] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: PMU: Add instruction and cycle events target/arm: PMU: Set PMCR.N to 4 target/arm: Implement PMSWINC target/arm: Mark PMINTENSET accesses as possibly doing IO target/arm: Send interrupts on PMU counter overflow target/arm/cpu.c | 49 +++- target/arm/cpu.h | 71 +++++- target/arm/cpu64.c | 2 - target/arm/helper.c | 702 +++++++++++++++++++++++++++++++++++++++++++++------- target/arm/kvm32.c | 27 +- 5 files changed, 720 insertions(+), 131 deletions(-) -- Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
