On 29 June 2018 at 01:15, Richard Henderson <richard.hender...@linaro.org> wrote: > For the supported extensions, fill in the appropriate bits in > ID_ISAR5, ID_ISAR6, ID_AA64ISAR0, ID_AA64ISAR1. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > ---
This makes sense, but I'd rather have a bit of time to think about how exactly we want to handle feature bits vs ID register values (the current codebase is not entirely coherent on the topic), so I'd rather not put this in for softfreeze unless there's a strong reason we should... thanks -- PMM
