On 07/10/2018 09:00 AM, Peter Maydell wrote: > The io_readx() function needs to know whether the load it is > doing is an MMU_DATA_LOAD or an MMU_INST_FETCH, so that it > can pass the right value to the cpu_transaction_failed() > function. Plumb this information through from the softmmu > code. > > This is currently not often going to give the wrong answer, > because usually instruction fetches go via get_page_addr_code(). > However once we switch over to handling execution from non-RAM by > creating single-insn TBs, the path for an insn fetch to generate > a bus error will be through cpu_ld*_code() and io_readx(), > so without this change we will generate a d-side fault when we > should generate an i-side fault. > > We also have to pass the access type via a CPU struct global > down to unassigned_mem_read(), for the benefit of the targets > which still use the cpu_unassigned_access() hook (m68k, mips, > sparc, xtensa). > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > accel/tcg/softmmu_template.h | 11 +++++++---- > include/qom/cpu.h | 6 ++++++ > accel/tcg/cputlb.c | 5 +++-- > memory.c | 3 ++- > 4 files changed, 18 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
