On 29 June 2018 at 14:29, Luc Michel <luc.mic...@greensocs.com> wrote:
> This commit improve the way the GIC is realized and connected in the
> ZynqMP SoC. The security extensions are enabled only if requested in the
> machine state. The same goes for the virtualization extensions.
> All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ,
> vIRQ and vFIQ. The missing CPU to GIC timers IRQ connections are also
> added (HYP and SEC timers).
> The GIC maintenance IRQs are back-wired to the correct GIC PPIs.
> Finally, the MMIO mappings are reworked to take into account the ZynqMP
> specificities. the GIC (v)CPU interface is aliased 16 times:
> * for the firsts 0x1000 bytes from 0xf9010000 to 0xf901f000
> * for the seconds 0x1000 bytes from 0xf9020000 to 0xf902f000
> Mappings of the virtual interface and virtual CPU interface are mapped
> only when virtualization extensions are requested. The
> XlnxZynqMPGICRegion struct has been enhanced to be able to catch all
> this information.
> Signed-off-by: Luc Michel <luc.mic...@greensocs.com>
Nothing obviously wrong here, but I'll leave the details for
one of the Xilinx folk to review.