On Tue, Jul 10, 2018 at 04:57:32PM +0800, Jingqi Liu wrote: > UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions. > > UMONITOR arms address monitoring hardware using an address. A store > to an address within the specified address range triggers the > monitoring hardware to wake up the processor waiting in umwait. > > UMWAIT instructs the processor to enter an implementation-dependent > optimized state while monitoring a range of addresses. The optimized > state may be either a light-weight power/performance optimized state > or an improved power/performance optimized state. > > TPAUSE instructs the processor to enter an implementation-dependent > optimized state c0.1 or c0.2 state and wake up when time-stamp counter > reaches specified timeout. > > The bit definition: > CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG > > The release document ref below link: > https://software.intel.com/sites/default/files/managed/c5/15/\ > architecture-instruction-set-extensions-programming-reference.pdf > > Signed-off-by: Jingqi Liu <jingqi....@intel.com>
Is it really OK to expose these features to the guest without "-overcommit cpu-pm=on"? Don't we need code to migrate IA32_UMWAIT_CONTROL? (I don't see code to handle writes to IA32_UMWAIT_CONTROL on the KVM patches, either.) -- Eduardo
