On 08/07/2018 09:57 AM, Joel Stanley wrote: > The SDRAM training routine sets the 'Enable cache initial' bit, and then > waits for the 'cache initial sequence' to be done. > > Have it always return done, as there is no other side effects that the > model needs to implement. This allows the upstream u-boot training to > proceed on the ast2500-evb board. > > Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric Le Goater <c...@kaod.org> Thanks, C. > --- > hw/misc/aspeed_sdmc.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c > index 24fd4aee2d82..9ece545c4ffa 100644 > --- a/hw/misc/aspeed_sdmc.c > +++ b/hw/misc/aspeed_sdmc.c > @@ -226,6 +226,7 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error > **errp) > s->ram_bits = ast2500_rambits(s); > s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) | > ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | > + ASPEED_SDMC_CACHE_INITIAL_DONE | > ASPEED_SDMC_DRAM_SIZE(s->ram_bits); > break; > default: >
