From: Aleksandar Markovic <amarko...@wavecomp.com> The following changes since commit 38441756b70eec5807b5f60dad11a93a91199866:
Update version for v3.0.0 release (2018-08-14 16:38:43 +0100) are available in the git repository at: https://github.com/AMarkovic/qemu tags/mips-queue-aug-14-2018 for you to fetch changes up to 20d4e01b6486b15d1f3d9ff2d51bba2bf00ebf94: qemu-doc: Amend MIPS-related items (2018-08-14 19:59:03 +0200) ---------------------------------------------------------------- MIPS queue for QEMU upstream, August 14, 2018 This is the first part of nanoMIPS support for QEMU. It contains various fixes and improvements that are related to nanoMIPS support, or are discovered while working on nanoMIPS support. Most of them are fairly simple changes, but each of them has its own significance and importance for nanoMIPS support. The second part that contains QEMU support for core nanoMIPS functionality will remain under review for some time. The third part that mainly contains Linux user support will likely remain under review for some longer period. ---------------------------------------------------------------- Aleksandar Markovic (9): MAINTAINERS: Update target/mips maintainer's email addresses target/mips: Avoid case statements formulated by ranges - part 1 target/mips: Mark switch fallthroughs with interpretable comments target/mips: Fix two instances of shadow variables target/mips: Update some CP0 registers bit definitions elf: Remove duplicate preprocessor constant definition elf: Add ELF flags for MIPS machine variants linux-user: Update MIPS syscall numbers up to kernel 4.18 headers qemu-doc: Amend MIPS-related items Aleksandar Rikalo (5): target/mips: Avoid case statements formulated by ranges - part 2 target/mips: Add support for availability control via bit XNP target/mips: Add support for availability control via bit MT target/mips: Fix MT ASE instructions' availability control linux-user: Add preprocessor availability control to some syscalls Stefan Markovic (3): target/mips: Add CP0 BadInstrX register target/mips: Implement CP0 Config1.WR bit functionality target/mips: Add gen_op_addr_addi() Yongbok Kim (2): target/mips: Don't update BadVAddr register in Debug Mode target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 .mailmap | 7 +- MAINTAINERS | 9 +- include/elf.h | 24 ++- linux-user/mips/syscall_nr.h | 9 + linux-user/mips64/syscall_nr.h | 18 ++ linux-user/strace.c | 14 +- linux-user/syscall.c | 29 +++ qemu-doc.texi | 13 +- target/mips/cpu.h | 162 ++++++++------- target/mips/helper.c | 4 +- target/mips/internal.h | 9 +- target/mips/machine.c | 5 +- target/mips/op_helper.c | 12 +- target/mips/translate.c | 443 ++++++++++++++++++++++++++++++++++------- 14 files changed, 598 insertions(+), 160 deletions(-) -- 2.7.4
