From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
When QEMU provides the equivalent of the EL3 firmware, we
need to enable HVCs in scr_el3 when turning on CPUs that
target EL2.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
target/arm/arm-powerctl.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index ce55eeb..54f2974 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -63,6 +63,7 @@ static void arm_set_cpu_on_async_work(CPUState
*target_cpu_state,
struct CpuOnInfo *info = (struct CpuOnInfo *) data.host_ptr;
/* Initialize the cpu we are turning on */
+ qemu_log("CPU%d reset\n", target_cpu_state->cpu_index);
cpu_reset(target_cpu_state);
target_cpu_state->halted = 0;
@@ -103,6 +104,16 @@ static void arm_set_cpu_on_async_work(CPUState
*target_cpu_state,
} else {
/* Processor is not in secure mode */
target_cpu->env.cp15.scr_el3 |= SCR_NS;
+
+ /*
+ * If QEMU is providing the equivalent of EL3 firmware, then we need
+ * to make sure a CPU targeting EL2 comes out of reset with a
+ * functional HVC insn.
+ */
+ if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3)
+ && info->target_el == 2) {
+ target_cpu->env.cp15.scr_el3 |= SCR_HCE;
+ }
}
/* We check if the started CPU is now at the correct level */
--
2.7.4
