> From: Yongbok Kim <yongbok....@mips.com> > > Add PWBase register (CP0 Register 5, Select 5). > > The PWBase register contains the Page Table Base virtual address. > > This register is required for the hardware page walker feature. It > exists only if Config3 PW bit is set to 1. > > Signed-off-by: Yongbok Kim <yongbok....@mips.com> > Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com> > ---
The only problem with this and subsequent register-related patches is that they do not bump version_id and minimum_version_id of vmstate_mips_cpu in machine.c, and they should. Other than this: Reviewed-by: Aleksandar Markovic <amarko...@wavecomp.com>
