On 10/12/18 7:42 AM, Peter Maydell wrote: > The HCR.DC virtualization configuration register bit has the > following effects: > * SCTLR.M behaves as if it is 0 for all purposes except > direct reads of the bit > * HCR.VM behaves as if it is 1 for all purposes except > direct reads of the bit > * the memory type produced by the first stage of the EL1&EL0 > translation regime is Normal Non-Shareable, > Inner Write-Back Read-Allocate Write-Allocate, > Outer Write-Back Read-Allocate Write-Allocate. > > Implement this behaviour. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > ---
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
