On 11 October 2018 at 03:19, Edgar E. Iglesias <edgar.igles...@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> > > This patch series adds initial support for Xilinx's Versal SoC. > Xilinx is introducing Versal, an adaptive compute acceleration platform > (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar > Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with > leading-edge memory and interfacing technologies to deliver powerful > heterogeneous acceleration for any application. The Versal AI Core series has > five devices, offering 128 to 400 AI Engines. The series includes dual-core > Arm > Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time > processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines > optimized for high-precision floating point with low latency. > > More info can be found here: > https://www.xilinx.com/news/press/2018/xilinx-unveils-versal-the-first-in-a-new-category-of-platforms-delivering-rapid-innovation-with-software-programmability-and-scalable-ai-inference.html
> Edgar E. Iglesias (12): > net: cadence_gem: Disable TSU feature bit > net: cadence_gem: Announce availability of priority queues > net: cadence_gem: Use uint32_t for 32bit descriptor words > net: cadence_gem: Add macro with max number of descriptor words > net: cadence_gem: Add support for extended descriptors > net: cadence_gem: Add support for selecting the DMA MemoryRegion > net: cadence_gem: Implement support for 64bit descriptor addresses > net: cadence_gem: Announce 64bit addressing support > target-arm: powerctl: Enable HVC when starting CPUs to EL2 > target/arm: Add the Cortex-A72 > hw/arm: versal: Add a model of Xilinx Versal SoC > hw/arm: versal: Add a virtual Xilinx Versal board Hi; this series is still on my to-review queue, but to start with I'm going to apply patches 1-10 (the cadence_gem fixes and the target/arm changes) to target-arm.next. thanks -- PMM
