On Wed, 31 Oct 2018 03:44:27 PDT (-0700), Bastian Koppelmann wrote:
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
[...]
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
I'm a bit confused here. According to the spec fclass_d is a RV32F
instruction but according to the original qemu code it is not?
fclass.d is part of the D extension, see section 9.7 of the user spec. It
should be present for all base ISAs when the D extension is present. The above
code is incorrect, but appears to be trivially fixable.
It looks like master is also incorrect, which I'm somewhat surprised about.
This might explain a whole host of 32-bit glibc floating-point test suite
failures...