Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Michael Clark <m...@sifive.com> --- tcg/riscv/tcg-target.inc.c | 81 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index e585740870..5319f7ade5 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -258,6 +258,87 @@ typedef enum { OPC_FENCE_RW_W = 0x0310000f, } RISCVInsn; +/* + * RISC-V immediate and instruction encoders (excludes 16-bit RVC) + */ + +/* Type-R */ + +static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; +} + +/* Type-I */ + +static int32_t encode_imm12(uint32_t imm) +{ + return (imm & 0xfff) << 20; +} + +static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); +} + +/* Type-S */ + +static int32_t encode_simm12(uint32_t imm) +{ + return ((imm << 20) >> 25) << 25 | ((imm << 27) >> 27) << 7; +} + +static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); +} + +/* Type-SB */ + +static int32_t encode_sbimm12(uint32_t imm) +{ + return ((imm << 19) >> 31) << 31 | ((imm << 21) >> 26) << 25 | + ((imm << 27) >> 28) << 8 | ((imm << 20) >> 31) << 7; +} + +static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); +} + +/* Type-U */ + +static int32_t encode_uimm20(uint32_t imm) +{ + return (imm >> 12) << 12; +} + +static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); +} + +/* Type-UJ */ + +static int32_t encode_ujimm12(uint32_t imm) +{ + return ((imm << 11) >> 31) << 31 | ((imm << 21) >> 22) << 21 | + ((imm << 20) >> 31) << 20 | ((imm << 12) >> 24) << 12; +} + +static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_ujimm12(imm); +} + +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) +{ + /* Note: jump target patching should be atomic */ + reloc_call((tcg_insn_unit *)jmp_addr, (tcg_insn_unit*)addr); + flush_icache_range(jmp_addr, jmp_addr + 8); +} + typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; -- 2.19.1