On 5 November 2018 at 18:52, Aaron Lindsay <aa...@os.amperecomputing.com> wrote:
> This both advertises that we support four counters and enables them
> because the pmu_num_counters() reads this value from PMCR.
>
> Signed-off-by: Aaron Lindsay <alind...@codeaurora.org>
> Signed-off-by: Aaron Lindsay <aa...@os.amperecomputing.com>
> ---
> target/arm/helper.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index e3ec36490c..11eb62bdda 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1753,7 +1753,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> .access = PL1_W, .type = ARM_CP_NOP },
> /* Performance monitors are implementation defined in v7,
> * but with an ARM recommended set of registers, which we
> - * follow (although we don't actually implement any counters)
> + * follow.
> *
> * Performance registers fall into three categories:
> * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
> @@ -5508,10 +5508,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> }
> if (arm_feature(env, ARM_FEATURE_V7)) {
> /* v7 performance monitor control register: same implementor
> - * field as main ID register, and we implement only the cycle
> - * count register.
> + * field as main ID register, and we implement four counters in
> + * addition to the cycle count register.
> */
> - unsigned int i, pmcrn = 0;
> + unsigned int i, pmcrn = 4;
> ARMCPRegInfo pmcr = {
> .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2
> = 0,
> .access = PL0_RW,
> @@ -5526,7 +5526,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .access = PL0_RW, .accessfn = pmreg_access,
> .type = ARM_CP_IO,
> .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
> - .resetvalue = cpu->midr & 0xff000000,
> + .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
> .writefn = pmcr_write, .raw_writefn = raw_write,
> };
> define_one_arm_cp_reg(cpu, &pmcr);
> --
With PMCR.N > 0, this means that MDCR_EL2.HPMN behaviour and
more generally support for the EL2 performance monitor trapping
options in MDCR_EL2 become relevant. But I think we're probably
best off leaving that for a future patchset.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
