> On 12/5/18 11:11 PM, Paul Burton wrote: > ATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for > all MIPS host builds, including those using the n32 ABI. n32 is the > MIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines > TCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU > for an n32 host with support for a 64b target architecture then > TCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use atomic_* > functions. This fails because ATOMIC_REG_SIZE is 4, causing the calls to > QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the various > atomic_* functions to generate errors. > > Fix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which > will cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as we > already do for x86_64/x32. > > Signed-off-by: Paul Burton <paul.bur...@mips.com>
I am going to include this patch in next mips pull request scheduled for today or tomorrow. Aleksandar
