On Fri, 11 Jan 2019 at 12:58, Cédric Le Goater <c...@kaod.org> wrote: > > The PHY behind the MAC of an Aspeed SoC can be controlled using two > different MDC/MDIO interfaces. The same registers PHYCR (MAC60) and > PHYDATA (MAC64) are involved but they have a different layout. > > BIT31 of the Feature Register (MAC40) controls which MDC/MDIO > interface is active. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> > ---
Applied to target-arm.next, thanks. -- PMM
