On Tue, Jan 22, 2019 at 1:52 PM Alistair Francis <alistai...@gmail.com> wrote: > You can get env and then check for floating point support: > > CPURISCVState *env = &cs->env; > if (env->misa_mask & RVF) { > ...
I needed this which wasn't hard to figure out. RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; if (env->misa & RVF) { The tricky bit was figuring out how to test it, because I wasn't sure if making registers conditional would actually work. I figured out that using -machine sifive_e gives me a target with no fpu, and playing with that a bit I get the expected result, which is that the FP regs don't print anymore. The FP related CSRs still do, but that would require gdb fixes I think, because gdb knows that they are both FP regs and CSR, and tries to print them both ways. That leads to a more general problem of figuring out exactly which CSRs a particular target implements, which is a bigger problem than I have time to fix at the moment, and should be handled as a separate problem. Since my patch set is now a month old, I'll rebase onto current master and post a version 3 patch set. Jim