On 01/02/2019 17:06, Peter Maydell wrote: > From: Remi Denis-Courmont <remi.denis.courm...@huawei.com> > > Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address, > extension (yet), the VA address space is 48-bits plus a sign bit. User > mode can only handle the positive half of the address space, so that > makes a limit of 48 bits. > > (With LVA, it would be 53 and 52 bits respectively.) > > The incorrectly large address space conflicts with PAuth instructions, > which use bits 48-54 and 56-63 for the pointer authentication code. This > also conflicts with (as yet unsupported by QEMU) data tagging and with > the ARMv8.5-MTE extension. > > Signed-off-by: Remi Denis-Courmont <remi.denis.courm...@huawei.com> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 63934a200ad..a68bcc9fedb 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -2512,7 +2512,7 @@ bool write_cpustate_to_list(ARMCPU *cpu); > > #if defined(TARGET_AARCH64) > # define TARGET_PHYS_ADDR_SPACE_BITS 48 > -# define TARGET_VIRT_ADDR_SPACE_BITS 64 > +# define TARGET_VIRT_ADDR_SPACE_BITS 48 > #else > # define TARGET_PHYS_ADDR_SPACE_BITS 40 > # define TARGET_VIRT_ADDR_SPACE_BITS 32 >
This change breaks qemu-aarch64 (using LTP test suite): # chroot chroot/arm64/bionic /opt/ltp/testcases/bin/access03 tst_test.c:1015: INFO: Timeout per run is 0h 05m 00s qemu-aarch64: .../qemu/accel/tcg/translate-all.c:2522: page_check_range: Assertion `start < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)' failed. qemu:handle_cpu_signal received signal outside vCPU context @ pc=0x60001554 Any idea? Thanks, Laurent
