The following changes since commit 061b51e9195670e9d190cdec46fabcb3c77763fb:
Update version for v4.0.0-rc2 release (2019-04-02 17:01:20 +0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-rc3-v2
for you to fetch changes up to 79bcac250f96ba1d4fdecfdc6e3363c9024703a4:
riscv: plic: Log guest errors (2019-04-04 16:36:21 -0700)
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RISC-V Patches for 4.0-rc3, v2
This patch set contains a pair of tightly coupled PLIC bug fixes:
* We were calculating the PLIC addresses incorrectly.
* We were installing the wrong number of PLIC interrupts.
The two bugs togther resulted in a mostly-working system, but they're
impossible to seperate because fixing one bug would result in
significant breakage. As a result they're in the same patch.
There is also a cleanup to use qemu_log_mask(LOG_GUEST_ERROR,...) for
error reporting.
As far as I know these are the last outstanding RISC-V patches for 4.0.
v2 no longer fails "make check" for me... sorry!
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Alistair Francis (2):
riscv: plic: Fix incorrect irq calculation
riscv: plic: Log guest errors
hw/riscv/sifive_plic.c | 16 +++++++++++-----
include/hw/riscv/sifive_e.h | 2 +-
include/hw/riscv/sifive_u.h | 4 ++--
include/hw/riscv/virt.h | 2 +-
4 files changed, 15 insertions(+), 9 deletions(-)
