On 5/23/19 8:46 AM, Peter Maydell wrote: > On Sat, 18 May 2019 at 20:19, Richard Henderson > <richard.hender...@linaro.org> wrote: >> >> This replaces 3 target-specific implementations for BIT, BIF, and BSL. >> >> Signed-off-by: Richard Henderson <richard.hender...@linaro.org> >> @@ -10916,13 +10925,13 @@ static void disas_simd_3same_logic(DisasContext >> *s, uint32_t insn) >> return; >> >> case 5: /* BSL bitwise select */ >> - gen_gvec_op3(s, is_q, rd, rn, rm, &bsl_op); >> + gen_gvec_fn4(s, is_q, rd, rd, rn, rm, tcg_gen_gvec_bitsel, 0); >> return; >> case 6: /* BIT, bitwise insert if true */ >> - gen_gvec_op3(s, is_q, rd, rn, rm, &bit_op); >> + gen_gvec_fn4(s, is_q, rd, rm, rn, rd, tcg_gen_gvec_bitsel, 0); >> return; >> case 7: /* BIF, bitwise insert if false */ >> - gen_gvec_op3(s, is_q, rd, rn, rm, &bif_op); >> + gen_gvec_fn4(s, is_q, rd, rm, rd, rn, tcg_gen_gvec_bitsel, 0); >> return; > > We were previously doing different operations for these three > different instructions. Now we seem to always be doing the same > thing but with randomly reshuffled register arguments. How > does this work ?
Because the three different instructions perform the same operation with reshuffled register arguments. I'm not sure why we were using different operations in the beginning. Possibly because those formulations do not require a temporary? Possibly that's how they're written in the ARM ARM pseudocode? r~
