On Sat, 25 May 2019 at 15:14, Cédric Le Goater <c...@kaod.org> wrote: > > Emulate read errors in the DMA Checksum Register for high frequencies > and optimistic settings of the Read Timing Compensation Register. This > will help in tuning the SPI timing calibration algorithm. > > The values below are those to expect from the first flash device of > the FMC controller of a palmetto-bmc machine. > > Signed-off-by: Cédric Le Goater <c...@kaod.org>
Reviewed-by: Joel Stanley <j...@jms.id.au>
