On Thu, 7 Mar 2019 at 17:05, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/cpu.h | 45 ++++++++++++++++++++++++++++++++++++++-------
> target/arm/helper.c | 20 +++++++++++++++++++-
> 2 files changed, 57 insertions(+), 8 deletions(-)
> /* Return the address space index to use for a memory access */
> static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
> {
> - return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
> + if (attrs.target_tlb_bit2) {
> + return ARMASIdx_TAG;
> + } else if (attrs.secure) {
> + return ARMASIdx_S;
> + } else {
> + return ARMASIdx_NS;
> + }
> }
Playing around with this series, I have discovered that if
the board model doesn't create the tag-memory then target/arm/cpu.c
will not create the 'cpu-tag-memory' AddressSpace. But nothing
disables the usage of the target_tlb_bit2, and then when
arm_cpu_tlb_fill() does a tlb_set_page_with_attrs() using
an attrs with target_tlb_bit2 set then we assert in
cpu_asidx_from_attrs() because cpu->num_ases is 2 and
cc->asidx_from_attrs() returned an out of range number (ie 2).
Is the tag-memory mandatory for MTE? If so we should either
disable MTE if no tag-memory is provided, or else fail
realize of the CPU; not sure which. If it's not mandatory
then we need to avoid asserting :-)
thanks
-- PMM
