On 7/25/19 11:46 PM, tony.ngu...@bt.com wrote: > No-op MEMOP_SIZE and SIZE_MEMOP macros allows us to later easily > convert memory_region_dispatch_{read|write} paramter "unsigned size" > into a size+sign+endianness encoded "MemOp op". > > Being a no-op macro, this patch does not introduce any logical change. > > Signed-off-by: Tony Nguyen <tony.ngu...@bt.com> > --- > accel/tcg/cputlb.c | 21 ++++++++++----------- > 1 file changed, 10 insertions(+), 11 deletions(-) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index 523be4c..5d88cec 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, > int size, > > static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > int mmu_idx, target_ulong addr, uintptr_t retaddr, > - MMUAccessType access_type, int size) > + MMUAccessType access_type, MemOp op)
As I mentioned for patch 2, don't change this now, wait until after patch 10. > - r = memory_region_dispatch_read(mr, mr_offset, > - &val, size, iotlbentry->attrs); > + r = memory_region_dispatch_read(mr, mr_offset, &val, op, > iotlbentry->attrs); So size_memop here, > - cpu_transaction_failed(cpu, physaddr, addr, size, access_type, > + cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op), > access_type, > mmu_idx, iotlbentry->attrs, r, retaddr); but no memop_size here. > static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > int mmu_idx, uint64_t val, target_ulong addr, > - uintptr_t retaddr, int size) > + uintptr_t retaddr, MemOp op) Likewise. > res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], > - mmu_idx, addr, retaddr, access_type, size); > + mmu_idx, addr, retaddr, access_type, > SIZE_MEMOP(size)); And when you do come back to change the types after patch 10, at the top of the function: - unsigned a_bits = get_alignment_bits(get_memop(oi)); + MemOp op = get_memop(oi); + unsigned a_bits = get_alignment_bits(op); and then pass along op directly. Which will fix some of the weirdness in patch 11. r~